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Samsung’s $40bn investment into chipmaking in Texas announced on Monday includes a plan to build an “advanced chip packaging” facility, that will bring the US a big step closer to being able to manufacture cutting-edge artificial intelligence chips on home soil.
The Korean company’s move is seen as a major win for the Biden administration which, alongside China, has recognised advanced packaging’s growing importance in the semiconductor supply chain.
The world’s leading chipmakers are pouring billions of dollars into expanding and improving advanced packaging techniques, believing they will be crucial to improving the performance of semiconductors.
What is advanced chip packaging?
As the process of miniaturising chips starts to reach its physical limits, chipmakers are being forced to identify alternative means to keep improving performance to match the increasingly intensive computing demands of technology such as generative AI.
By integrating or “packaging” multiple chips — whether of the same kind or different varieties — more closely together, chipmakers can increase speed and efficiency while circumventing the limits of miniaturisation.
What are examples of advanced packaging?
High bandwidth memory (hbm)
High-performance chips such as Nvidia’s graphics processing units (GPUs) require a tremendous amount of memory to store their calculations. Even the most advanced memory chips do not by themselves offer sufficient “bandwidth” for the calculations to be stored and sent back and forth as required.
High bandwidth memory chips are produced by stacking Dram memory chips and connecting them with tiny wires running through small holes in each layer, like a multistorey library with a lift swiftly transporting large volumes of books between floors for collection and delivery.
chIP-ON-WAFER-ON-SUBSTRATE (CoWoS)
In the case of Nvidia’s H100 “Hopper” AI chip, six HBM chips are integrated with an Nvidia-designed and TSMC-produced GPU, using the Taiwanese manufacturer’s “Chip-on-Wafer-on-Substrate” (CoWoS) advanced packaging technique.
The GPU and the HBM chips both sit on a silicon interface known as an “interposer”, through which they communicate with one another. The interposer then sits on a base layer, or “substrate”. TSMC’s rivals Samsung and Intel have their own names for similar versions of the same technique.
It is sometimes referred to as a “2.5D” advanced packaging technique, because while the Dram layers in the HBM are stacked, the HBM chips and GPU sit alongside one another. Samsung’s new facility in Texas will be able to do both 2.5D and HBM packaging, while fellow Korean chipmaker SK Hynix is building an HBM plant in Indiana.
“3D packaging” in this context would involve vertical integration of the HBM and GPU components, but engineers are yet to figure out how to keep such a system sufficiently cooled and powered.
integrated fan-out (info)
Advanced packaging is also useful when a chip is operating within strict physical limits. Chips used in smartphones are a good example, because logic chips cannot get much smaller, and smartphones cannot get much bigger.
In 2017, Taiwanese chipmaker TSMC, together with Apple, introduced a new advanced packaging technique called Integrated Fan-Out. This involves integrating logic and memory chips closer together through a new high-density “redistribution layer”, improving performance while removing the need for a thicker base layer.
What are the implications for the industry?
Advanced packaging requires greater co-operation between industry specialists.
TSMC, for example, which has no background in memory chip production, works closely on Nvidia’s AI chips with HBM market leader SK Hynix, which has no background in logic chip production.
Samsung Electronics and Intel, meanwhile, have a record in both logic and memory as well as advanced packaging, meaning they will potentially be able to offer customers integrated services across all three areas.
The growth in importance of advanced packaging also offers an opportunity for second-tier chipmakers and traditional packaging companies, all of which are investing in their own advanced packaging capabilities, to gain a larger share of the $500bn semiconductor market.
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